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ML/AI Approach to Design Implementation

A free, half-day workshop
(limited seating)

Join us for a deep dive into Cadence Cerebrus, an AI-enabled chip design optimization tool that provides improved power, performance, and the area along with a 10x to 20x productivity boost by leveraging machine learning for synthesis, place, and route. 

9 a.m.–12:30 p.m.,  Wednesday, April 26, 2023

UCSC Silicon Valley Extension
3175 Bowers Ave., Santa Clara, CA 95054
This is an in-person workshop.

NOTE: Attendees need to bring laptops to participate in the exercises.
 


This event is sponsored by the UCSC Silicon Valley Extension VLSI Engineering program. Please reach out with questions: extension@ucsc.edu.