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ASIC Design Using OpenROAD

A free, half-day workshop
(limited seating)

Knowing how to use open EDA tools boosts your career prospects in the exponentially growing semiconductor industry!

In this workshop, you’ll:

Explore the design space for QoR estimation and implementation.
Analyze key design parameters early in the RTL design phase for fast convergence to performance, power and area targets.
Leverage the cloud and other collaborative tools to optimize computational resources for fast run times and efficiency.

9 a.m. – 1 p.m., Saturday, April 15, 2023

UCSC Silicon Valley Extension
3175 Bowers Ave., Santa Clara, CA 95054
This is an in-person workshop.

This event is sponsored by the UCSC Silicon Valley Extension VLSI Engineering program. Please reach out with questions: extension@ucsc.edu.

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